MODES

• Legacy I2C Mode (5 MHz)
• I3C SDR mode (15 MHz)
• I3C HDR-DDR mode (15 MHz)
• I3C SDR Multilane Mode (15 MHz)

FUNCTIONAL TESTS

• Register Write (Legacy I2C /SDR/HDR)
• Register Read (Legacy I2C /SDR/HDR)
• Write N Bytes (Legacy I2C /SDR/HDR)
• Read N Bytes (Legacy I2C /SDR/HDR)
• Write N – Read N Bytes (Combined Format) (Legacy I2C /SDR/HDR)​
• Hot-Join Functional Test
• IBI Functional Test
• IBI Interrupt Spacing Tests ​
• Clock Stalling ​
• Conformance Test Suite (CTS)

DEVICE MODES

• Target (Slave)
• Control (Master)

PROTOCOL FEATURES

• Dynamic/Static Addressing
• Direct and Broadcast CCC Commands
• START / STOP Conditions
• Address Header and Transition Bit
• HDR DDR Restart and Exit Patterns
• Target Reset Pattern
• Group Target Addressing

FAULT TESTS

• Induce SDR Errors (S0-S5) & (CE0-CE2)
• Induce HDR DDR Errors
• Skip Start / Stop / Repeated Start
• Skip HDR Restart / HDR Exit
• Add clocks from address/data bytes
• Skip clocks from address/data bytes
• Induce Parity/Preamble Errors
• Induce Errors in CRC5 Calculation
• Any custom faults in SDR/ HDR DDR transactions and can check if the Target is able to recover from the faults.

I2C Legacy Timing Parameters​

• fSCL SCL Clock Frequency​
• tSU_STA Setup time for Repeated Start
• tHD_STA Hold time for a (Repeated) start
• tLOW SCL Clock Low Period
• tHIGH SCL Clock High Period
• tSU_DAT Data Setup Time
• tHD_DAT Data Hold Time
• trCL SCL signal Rise time
• tfCL SCL signal Fall time
• trDA SDA signal Rise time
• tfDA SDA signal Fall time
• tSU_STO Setup time for Stop
• tBUF Bus Free time between a Stop and a Start
• tSPIKE Pulse width of spikes to supress
• tDIG_H Digital SCL Clock High Period
• tDIG_L Digital SCL Clock Low Period
• tTIMEOUT – Detect Clock Input Low Time
• tDOUT – SCL Falling Clock In to valid SDA Output Time

Electrical IO Parameters​

• VIL Low-Level Input Voltage
• VIH High-Level Input Voltage​
• Vhys Schmitt Trigger Inputs Hysteresis​
• VOL Output Low Level
• VOH Output High Level

I3C Push-Pull Timing Parameters​

• fSCL SCL Clock Frequency​
• tLOW_PP SCL Clock Low Period​
• tHIGH_PP SCL Clock High Period
• tSCO Clock into Data out for responder
• tCR SCL Clock Rise Time​
• tCF SCL Clock Fall Time
• tHD_PP SDA signal Data Hold in Push-pull mode
• tSU_PP SDA signal Data Setup in Push-pull mode
• tCASr Clock after Repeated start condition​
• tCBSr Clock before Repeated start condition​
• tDIG_H Digital SCL Clock High Period
• tDIG_L Digital SCL Clock Low Period

Open-Drain Timing Parameters​

• tLOW_OD Low period of SCL clock​
• tHIGH_OD High period of SCL clock​
• tfDA_OD Fall time of SDA signal​​
• tSU_OD Data setup time during open-drain mode​
• tCAS Clock after start condition​
• tCBP Clock before stop condition
• tAVAL Bus Available Condition
• tIDLE Bus Idle Condition​
• tDIG_H Digital SCL Clock High Period
• tDIG_OD_L Digital SCL Clock Low Period

Other Parameters​

• tDOFFS -SCL Rising Clock In to Target SDA Output Off
• tDOFFM – SCL Rising Clock In to Master SDA Output Off
• tCL_r_DAT_f – SCL Rising Clock In to Master Driving Data Signal Low
  tIBI_ISSUE – Time to issue IBI after an event is detected when Bus is available
• tCLR_I3C_CMD_ Delay – Time from Clear Register Status to any I3C operation with Start condition to avoid false IBI generation
• tDEVCTRLCCC_ DELAY_PEC_DIS – DEVCTRL CCC Followed by DEVCTRL CCC or Register Read/Write Command Delay
• tWR_RD_DELAY _PEC_EN – Register Write Command Followed by Register Read Command Delay in PEC Enabled Mode
• tI3C_CCC_Update _Delay – RSTDAA CCC or ENEC CCC or DISEC CCC to any other CCC or Read/Write Command Delay
• tCCC_Delay – Any CCC followed by RSTDAA CCC delay